Building an HDMI capture board with the MS2109

Introduction

I wanted to build my own HDMI capture board.

There’s no cost argument for it at all: a commercial dongle sells for somewhere in the 1000-yen range. What I wanted was to know what’s inside one, and how much of it I could build myself.

This article records things in the order I tried them. The things that didn’t work, and the mistakes I caught partway through and fixed, are still in here — I didn’t delete them. I think it’ll be more useful to someone who wants to see the shape of the process than to someone building the exact same thing.

Every part I picked is something JLCPCB has in stock. I wanted to cut down on hand soldering, and when you’re only building one board, sourcing parts is the biggest cost there is.

👇 The PCB from a commercial dongle I took apart

What I ended up with/Schematic

The board takes video in on HDMI Type-A and streams it to the PC as a USB 2.0 UVC device. From the PC’s side it looks like an ordinary webcam.

Parts used

20 types and 51 placements in all; the parts came to about $5.5 per board.

The board

4-layer board, 1.6mm thick, built on JLCPCB’s standard stackup JLC04161H-7628.

Why I went with the MS2109

Listing the candidates and checking stock

I went and looked at JLCPCB’s assembly stock for real, and narrowed things down from there.

USB 3.0 on the MS2130 was tempting, but a 9mm-square QFN-64 raises the difficulty of the board, and for a first attempt I wanted to prioritize getting something that works — so I went with the MS2109.

The MS2106E is for analog (composite / S-Video) input, which is the wrong direction for me. It wasn’t on JLCPCB’s assembly parts list either, so choosing it would have meant hand soldering.

Designs I referred to

• YuzukiHD/YuzukiHCC — an open-source MS2109 design (CERN-OHL-P). Gerbers and BOM are all there
• BertoldVdb/ms-tools — a tool for reading and writing the MS2109’s EEPROM (MIT)

I designed against the datasheet’s application circuit and these two side by side.

Key points of the circuit

Two power rails: 3.3V and 1.2V

From the 5V on USB VBUS, SY8089A1AACs make 3.3V and 1.2V.

Making the 1.2V with a linear regulator would mean (5−1.2)×0.25A ≒ 0.95W of loss and the heat that comes with it, so this one has to be a switcher.

The SY8089A1AAC’s reference is 0.6V, and the output is Vout = 0.6 × (1 + RH/RL).

I put a 270pF Cff across RH, the upper resistor of the divider. Silergy’s application note recommends Cff=22pF for RH=100kΩ, but I scaled RH down to the 10kΩ range to match resistor values I already had, so I scaled Cff up by 10× too, to keep the zero in the same place.

The 3.3V splits three ways through ferrites

The MS2109 has three separate kinds of 3.3V supply pins.

AVDD33 is the analog supply for the TMDS input stage, so it gets isolated from digital noise. V33USB is for the USB PHY only, and the datasheet says outright: “100nF + 10µF right next to the pin.”

AVDD12 and DVDD12, on the other hand, don’t need to be separated. The datasheet’s application circuit also ties pins 19 / 27 / 33 / 41 all to a single net called VDD12.

Decoupling goes per pin, not per rail

This is a part I recounted and fixed partway through the design.

Even on the same rail, you put one capacitor per supply pin. The point of decoupling is to kill the inductance of the current loop as seen from that pin, so a few millimetres away from the pin it stops working.

Laying out where the MS2109’s supply pins sit on the QFN, it came out like this.

The 1.2V is a single rail, but pin 19 is on the bottom edge and pin 41 on the top, on opposite sides of the package, so two isn’t enough — you need four.

AVDD33 is scattered across three sides too, so it needs three. My first schematic had one here, and I caught it on review.

The HDMI input

The +5V detect isn’t divided down. The 5V on connector pin 18 goes straight into HDRXDET through a 1kΩ. The design relies on the MS2109’s internal clamp plus the 1kΩ to limit the current, exactly as in the datasheet’s application circuit.

The crystal has four pads

X322524MOB4SI is an SMD3225-4P. I’d drawn it assuming two terminals, then noticed partway through and fixed it.

2 and 4 are shield terminals internally connected to the metal lid. Leave them floating and the lid acts as an antenna, which hurts the stability of the oscillator.

For the 12pF×2 load capacitors, the datasheet’s application circuit marked them NC, so I was going to DNP them at first, but I ended up fitting them. With 12pF of load capacitance on a CL=12pF crystal the frequency comes out a few tens of ppm high, but that’s not a problem for USB video.

USB goes to a 4-pin header

I dropped the Type-C receptacle and used a 2.54mm 1×4 pin header instead. The pin order is 1=VBUS / 2=D− / 3=D+ / 4=GND.

That matches the wire colour order of a USB-A cable (red, white, green, black) exactly, so if you cut up a commercial USB cable and solder it straight on, it maps 1:1.

Dropping Type-C also got rid of the two CC1/CC2 pull-down resistors.

Reusing parts from a board I built before

I had the BOM of another board I’d built previously (one with PoE and DDR4 on it) on hand, so I cross-checked against it. The result: 13 of the 20 types could be reused at the same LCSC part number.

The best hit was the ESD array. I’d used the TPD4E05U06DQAR on the previous board, and it worked for TMDS as-is. It’s a part TI explicitly calls out for HDMI 2.0 in the datasheet.

I changed the design in two places to suit the reuse.

• CC resistors from 5.1kΩ to 4.7kΩ — Rd in the USB-C spec is 5.1kΩ ±20%, so that’s in range (and since I dropped Type-C in the end, it turned out not to be needed)
• FB divider from 100k/22k to 10k/2.2k — both values I already had

The parts cost went from $4.73 to $5.56, up $0.83. The Murata capacitors and the 4×4mm inductor are pricier than generic parts. It comes down to whether you’d rather standardize on fewer part numbers or keep the cost down.

The crystal I couldn’t reuse, because the previous board had an X322525MOB4SI (25MHz) and the frequency is different — but the X322524MOB4SI I picked is the 24MHz version of the same series from the same maker, YXC. The footprint and library carried over unchanged.

Board design rules

JLCPCB’s manufacturing limits and the practical line below which you don’t pay extra are two different things.

Manufacturing limits

Where the extra charges start

• Trace width/clearance of 3.0–3.5 mil → +20% of the order total on 4- to 8-layer boards
• Via holes under 0.3 mm → more expensive than standard

So if you stay within 5mil / 5mil and 0.3mm vias, there’s no extra charge.

What actually binds is impedance

On the 4-layer standard stackup JLC04161H-7628, the prepreg between L1 and L2 is 0.2104mm (Dk=4.4). Routing on L1 over that, the trace widths you need come out like this.

Those are far wider than the 0.09mm minimum, so minimum trace width isn’t the bottleneck. The design problem isn’t being able to route thin — it’s finding the space to route at the width the impedance requires.

You can’t do this on 2 layers

For reference, here’s what the trace widths look like if you try the same thing on 2 layers.

The MS2109 is a QFN-48 on a 0.5mm pitch with 0.25mm pads. On 2 layers you’d be connecting a trace eight times the width of the pad to a 0.25mm pad, which you simply can’t draw.

On top of that, the datasheet asks for “no routing on the layer directly under the differential traces, solid GND instead” — so if you make the whole back side of the signal layer GND on a 2-layer board, there’s no layer left to run four power rails on.

Vias

For the thermal vias in the MS2109’s EP I used 0.3mm holes / 0.6mm pads, 3×3 on a 1.2mm pitch. The EP is 5.3mm square, so they fit with room to spare.

I put no vias in the TMDS or USB differential traces. The datasheet says “two vias or fewer,” but zero is ideal.

Bringing up the board when it arrived

The board as it arrived from JLCPCB

What I did before applying power

A multimeter was the only test gear I had, so I made the pre-power checks thorough.

First I checked the part count and orientations by eye. Pin 1 markings on the QFNs, IC orientation, anything that didn’t get placed — a pass over all of it.

Next, measurements on the multimeter’s resistance range, with no power applied.

On the continuity range, I checked that 3V3↔A3V3 and 3V3↔V33USB do beep (the ferrites’ DCR) and that 3V3↔1V2 doesn’t.

I’d brought test points out on every rail, which made this part easy.

First power-up on a USB charger

HDMI stays unplugged. This board is powered from USB VBUS alone, and the +5V on the HDMI side is only used as a detect input and as the source for the DDC pull-ups, so plugging in HDMI by itself does nothing.

Worse, plugging HDMI in first means the source’s +5V goes into HDRXDET through a 1kΩ while the MS2109’s supplies are still at 0V. Putting voltage on an unpowered IC is how you get latch-up.

Before plugging it into the PC, I powered it from a USB charger. Checking the power rails only needs VBUS, so a charger with no data lines connected is plenty. If something were shorted, the only thing that breaks is the charger.

The voltages came out like this.

All five points were in range.

Plugging it into the PC

I’d fitted the EEPROM blank, so the question was whether it would come up on the default settings in the MS2109’s internal ROM.

Here’s what USB Device Tree Viewer showed.

Vendor ID                : 0x534D (Hefei Macrosilicon Technology Co., Ltd.)
Product ID               : 0x2109
Manufacturer String      : "MACROSILICON"
Product String           : ---
USB Version              : 2.0 (480 Mbit/s)
Device Connection Speed  : High-Speed
Video                    : UVC Version 1.00
                 -------- Default Video Modes --------
1920 x 1080 @ 30 fps     : MJPEG
1920 x 1080 @ 5 fps      : YUY2
1600 x 1200 @ 30 fps     : MJPEG
1600 x 1200 @ 5 fps      : YUY2
1280 x 1024 @ 30 fps     : MJPEG
1280 x 1024 @ 8 fps      : YUY2
1280 x 960 @ 30 fps      : MJPEG
1280 x 960 @ 8 fps       : YUY2
1360 x 768 @ 30 fps      : MJPEG
1360 x 768 @ 8 fps       : YUY2
1280 x 720 @ 30 fps      : MJPEG
1280 x 720 @ 10 fps      : YUY2
1024 x 768 @ 30 fps      : MJPEG
1024 x 768 @ 10 fps      : YUY2
800 x 600 @ 30 fps       : MJPEG
800 x 600 @ 20 fps       : YUY2
720 x 576 @ 30 fps       : MJPEG
720 x 576 @ 25 fps       : YUY2
720 x 480 @ 30 fps       : MJPEG, YUY2
640 x 480 @ 30 fps       : MJPEG, YUY2

What I could read out of that.

• Device Connection Speed is High-Speed — the D± routing and impedance are fine
• Product String is empty — confirms the EEPROM is unwritten (as planned)
• The resolution list matches datasheet §6.4 Table 6.3 exactly — the ROM is booting properly and emitting the right UVC descriptors

With an HDMI source connected, I got 1920×1080@30 video.

Chasing down the noise in the video

I had video, but there was coloured noise on the picture.

Capturing the PC desktop, small text came out stained magenta and cyan. I wanted to separate bad TMDS routing from USB transfer errors, so I went and looked at the pixel values in the captured image.

Looking at the numbers

The black text is perfectly neutral. If one of the TMDS channels were down, there’d be colour here.

In the magenta areas R and B are almost identical (246 and 247) and only G is about 80 lower. And the mean of R − B is −0.2 — meaning R and B track each other perfectly.

On top of that, zooming in on large text, the edges are pure black with no colour fringing at all. White backgrounds stayed pure white too.

In other words, luma (Y) is completely intact, and only the chroma (Cb/Cr) is breaking down, and only where the text is fine.

If there were a problem with the TMDS routing or impedance, you’d see sparkle or horizontal streaking on large black fills and edges as well. If it were a USB transfer error, flat white areas would break up in blocks too. Neither was happening.

It was MJPEG compression

To push 1920×1080@30 through USB 2.0, the MS2109 compresses with MJPEG.

• Uncompressed, that’s 1920×1080×2byte×30fps = 124 MB/s (about 1Gbps)
• The usable bandwidth of USB 2.0 High-Speed is about 20 MB/s
• So the compression ratio is about 6:1

On live-action footage 6:1 is essentially lossless, but on fine text it bites. Chroma subsampling sits on top of that, so colour information is the first thing sacrificed. Magenta and cyan alternating is exactly what that failure mode looks like.

And what I was displaying this time was a PC desktop: small text tiled across the whole screen, the worst possible subject for MJPEG.

The resolution list had the answer all along

Once I’d figured that out, I went back and looked at the UVC resolution list, and there was a pattern to the frame rates attached to the YUY2 (uncompressed) modes.

They all land at about 18–21 MB/s. That’s the ceiling of USB 2.0 High-Speed’s usable bandwidth, and MacroSilicon had picked the fps values to fit inside it.

What to do about it

Use a YUY2 mode and you get lossless capture.

Commercial MS2109 dongles show the same symptom, so there was nothing particularly wrong with this board.

If you want to solve it properly, the only option is the USB 3.0 MS2130.

Things I haven’t checked yet

• Writing the EEPROM — the Product String is still empty. Write it with ms-tools and the product name and EDID can be my own. The image quality won’t change, though (the compression ratio is set by the bandwidth)
• Audio — whether it shows up as a UAC device
• Four simultaneous captures — from what I’ve read, the UVC isochronous bandwidth reservation looks like the wall here. USB 2.0 can allocate 384Mbps to isochronous traffic, while a single UVC device declares a maximum of 196Mbps. One device takes half the budget, so a second one just barely fits and a third gets rejected outright. The awkward part is that the reservation is made against the declared figure, not what’s actually consumed

Summary

• Checking JLCPCB’s stock one part at a time means nothing stalls when you place the order
• Cross-checking against the BOM of a board I’d built before, 13 of the 20 types could be reused at the same part number
• A datasheet’s application circuit looks like just a schematic, but the design intent shows up in how the nets are named (VDD12 as a single net, AVDD33 and DVDD33 kept separate)
• Do the first power-up on a USB charger. There’s no reason to put a PC port at risk
• The noise in the video wasn’t a board fault, it was MJPEG compression. Measure the pixel values and you can tell the cause apart by whether it’s luma or chroma that’s broken

I think the reason my first 4-layer board worked on the first try is that I followed §11 of the datasheet, “PCB Design Notes,” without arguing with it. Differential impedance, the number of vias, and not splitting the solid GND. Keep those three and even an amateur can get signals through at HDMI speeds.

Reference links

• MacroSilicon MS2109 datasheet
• YuzukiHD/YuzukiHCC — open-source MS2109 design
• BertoldVdb/ms-tools — analysis of the MS2106/MS2109/MS2130 and EEPROM writing
• TPD4E05U06 datasheet (TI)
• Controlled Impedance PCB Layer Stackup (JLCPCB)
• PCB Capabilities (JLCPCB)
• Multiple UVC cameras on Linux: an unexpected challenge
• USB Device Tree Viewer